The invention pertains to computer data storage device controllers and, more specifically, pertains to a RAID controller having a host interface that emulates ATA standard controllers and attached IDE devices.
The first IBM PC and compatibles had only floppy disk drives for mass storage. The XT and AT models that followed included adapters for the connection of 5.25 inch fixed disks (non-removable) for mass data storage. These original adapters provided most of the low-level control signals for the drives including data separation circuits for the read signals and pre-compensated write signals. Including these functions in the adapter avoided replication in a pair of drives that were accessed only one at a time. Unfortunately, the 5 M bit read/write channel on the adapter did not allow faster drives to be attached as the technologies improved.
Moving the xe2x80x9creal timexe2x80x9d aspects of the controller into the drive solved this problem. The Integrated Drive Electronics or IDE drive incorporates all of the controls and data channel necessary to read or write the drive, transferring data between a local buffer and the media. The manufacturer may choose the data rate. A new interface, the ATA (AT Attachment with Packet Interface Extension (ATA/ATAP1-4)) (IBM AT Attachment Interface) was defined for the connection of data storage devices to the host system. The first IDE interfaces consisted of little more than address decoding and buffering between the ISA Bus and the ATA cable connector. The interface protocol used programmed input and output instructions to access the registers of the IDE device. Data transfers used the host processor""s input string and output string instructions throttled to the transfer rates of the attached drives. These transfer rates reached 16 Mbytes per second in the later revisions of the specification. This was the transfer rate between the buffer on the storage device and memory on the ISA Bus. The transfer rates between the media and the buffer we much lower.
With the advent of the PCI Bus, Intel published the PCI IDE document (PCI IDE Controller Specification, Revision 1.0, Mar. 16, 1994) which provided a standard mapping of the previously ISA Bus based host interface to the PCI Bus. The standard described a Dual IDE Channel Controller. A pair of devices, the Master and the Slave, could be attached to each of the channels. For data transfers, the device was still accessed as a PCI Bus Target.
Intel also published the Bus Master IDE document (Programming Interface for Bus Master IDE Controller, Revision 1.0, May 16, 1994). This document defines a standard for the incorporation of DMA devices within the IDE channels. The Bus Mastering interface allows the IDE channel to transfer data over the PCI Bus to or from system memory as a Bus Master (PCI Bus Initiator). The peak transfer rate to a 32 bit/33 MHz PCI Bus is 133 Mbytes per second.
A revision of the ATA specification defined a new transfer mode, Ultra DMA. Prior transfer rates improvements had been obtained by tightening the setup and hold time requirements for data transfers on the cable. At 16 Mbytes per second, the read transfer rate was very much limited by the round trip of sending out the read strobe, accessing the data, and sending back the data. The Ultra DMA protocol initially retained the electrical characteristics of all of the signal and cable, simply redefining the functions of three of the signals to provide a new protocol. In this protocol, the strobe signal that provides the data timing is sent from the same end as the data, i.e., by the controller for a write and by the device for read. In this configuration, the transfer rate is limited only by the cable skew for a single transition of the cable. The first UDMA devices double the programmed IO transfer rates to 33 Mbytes per second. Subsequent revisions double the initial UDMA transfer rate to 66 Mbytes per second, but required the use of an 80 conductor ribbon cable with alternating signal and ground conductors. The current version supports transfer rates of 100 Mbytes per second. There is currently a move afoot to replace the ATA Parallel interface with a high speed serial link, but it is possible that one more parallel speed increment may be released first.
The Problem
The common personal computer consists of a motherboard that is designed around a chip-set which includes a processor, a DRAM interface, various Input/Output adapters, and a BIOS ROM. The IO adapters generally include an IDE interface. Current versions of IDE controllers feature a pair of IDE ports, each capable of interfacing to a pair of IDE storage devices. These devices typically include one or more IDE hard disks plus CD ROM, DVD ROM, or CD WORM drives. The Basic Input Output System or BIOS is a program that is used to boot the PC and to provide low level IO routines for the adapters on the motherboard. Essentially all of these PC""s can boot and run from an IDE hard disk using the motherboard BIOS.
Increasingly, personal computers are deployed in server or workstation applications in the Small Office/Home Office (SOHO) marketplace. Historically, hard disks with the Small Computer System Interface (SCSI) provided some performance gains for these more demanding applications. Today, however, with more than 85% of all drives being produced as IDE drives, the SCSI drives tend to be built using the same media and read/write heads with little or no performance gains and greatly increased cost. Another popular alternative is to utilize a Redundant Array Of Inexpensive Disks (RAID) as originally proposed by Patterson (D. Patterson, et al., xe2x80x9cA Case for Redundant Arrays of Inexpensive Disks (RAID)xe2x80x9d (Univ. Cal. Report No. UCB/CSD87/391, December 1987). RAID systems address both the reliability and the performance issues. First, reliability is obtained by storing the data redundantly over two or more drives so that no data is lost if a single drive fails. Second, increased performance is obtained relative to that of a single drive because of the aggregate performance of the array. Different sections of data stored redundantly may be read concurrently from two drives. Also, data may be written in stripes which cross all of the available drives so that the aggregate transfer rate can be realized when the data is read back. RAID array controllers are further described in the present inventor""s U.S. Pat. No. 6,018,778.
Unfortunately, there are disadvantages to the several RAID solutions available. Local intelligence and the use of SCSI disk drives characterize one class of RAID solution. This class exhibits high performance albeit at very high cost for both the drives and the controller. The other popular RAID solution class is characterized by the use of IDE drives and the lack of any local intelligence or buffering. This is essentially a software solution. The software necessary to control the multitude of drives to maintain redundancy or to stripe data must all run on the host system, greatly increasing the disk drive overhead on the processor and the system bus. Thus RAID benefits are achieved at the cost of reduced system performance due to this increased overhead. Both of these solutions share an additional problem. These RAID controllers are not supported directly by the BIOS on the motherboard. Additional software drivers are required. These drivers may vary as a function of the operating system, e.g., Windows, Windows NT, UNIX, LINUX, etc resulting in an additional burden for the controller manufacturer, OEMs, marketing groups, and system integrators.
The need remains, therefore, for a RAID storage device controller that does not require special software to execute on the host processor, and does not require additional software drivers or changes to the BIOS. A RAID controller that requires no changes to the BIOS would have the advantage of xe2x80x9cplug-and-playxe2x80x9d compatibility with virtually all standard, off-the-shelf computers that implement an ATA compliant interface. The RAID controller would be transparent to the host, and could be used to deploy multiple storage devices (not limited to four), in any combination of device interfaces, and could implement RAID mirroring, striping, etc. without adding overhead to the host. Such a RAID controller would bring RAID capability to all PC users at low cost and with very simple installation.
The current invention implements a RAID controller that is compatible with all operating systems than can boot and run on a given PC motherboard using a standard IDE controller and IDE drive. It achieves this compatibility by emulating the standard controller and attached drive. For example, a given system might require a pair of drives in a RAID1 or xe2x80x9cmirroringxe2x80x9d configuration for reliability. When connected to the controller described in the current invention, the BIOS will see a single, very reliable drive. The same system might also require an array of three drives configured as either a RAID3 or RAID5 configuration. This would provide twice the transfer rate of any one of the three drives with high reliability. Once again, on the current invention, this array of three drives would appear to the BIOS as a single drive reporting twice the capacity of any one of the three drives and exhibiting twice the transfer rate with high reliability. In any case, the RAID is transparent to the existing drivers in the BIOS.
The controller of the current invention emulates the standard two-channel IDE controller. Like the standard controller, it is logically connected to the PCI Bus. It may reside either physically on the motherboard, possibly integrated within the motherboard chip-set, or on a plug-in card in a PCI slot. It may emulate all four devices that might be attached to the standard controller. Each of these logical devices provides a potential interface to an array of physical devices attached to the controller. While the current embodiment provides ATA ports for the attachment of the physical drives, other types of interfaces or combinations of interfaces might be used.
Additional objects and advantages of this invention will be apparent from the following detailed description of preferred embodiments thereof which proceeds with reference to the accompanying drawings.